Wehmeyer / Marwedel Fast, Efficient and Predictable Memory Accesses

Optimization Algorithms for Memory Architecture Aware Compilation
1. Auflage 2006
ISBN: 978-1-4020-4822-7
Verlag: Springer Netherland
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 258 Seiten, eBook

Fast, Efficient and Predictable Memory Accesses

presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

Zielgruppe

Research

Autoren/Hrsg.

Wehmeyer, Lars

Marwedel, Peter

Inhaltsverzeichnis

Abstract.- Models and Tools.- Scratchpad Memory Optimizations.- Main Memory Optimizations.- Register File Optimization.- Summary.- Future Work.

Über Autor(innen)

Prof. Peter Marwedel is well established within the Electronic Design Automation community, he has co-authored four books with us and also published his best-selling Embedded Systems Design (text)book with Springer.