Flip-Flop Design in Nanometer CMOS

From High Speed to Low Energy
2015
ISBN: 978-3-319-01996-3
Verlag: Springer International Publishing

Buch, Englisch, 260 Seiten, HC gerader Rücken kaschiert, Format (B × H): 160 mm x 241 mm, Gewicht: 5884 g

This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate  and postgraduate students (already familiar with digital circuits and timing).

Zielgruppe

Research

Autoren/Hrsg.

Alioto, Massimo

Palumbo, Gaetano

Consoli, Elio

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf

Inhaltsverzeichnis

The Logical Effort Method.- Design in the Energy-Delay Space.- Clocked Storage Elements.- Flip-Flop Optimized Design.- Analysis and Comparison in the Energy-Delay-Area Domain.- Energy Efficiency Versus Clock Slope.- Hold Time Issues and Impact of variations on Flip-Flop Topologies.- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies.