Emerging Technology and Architecture for Big-data Analytics

Softcover Nachdruck of the original 1. Auflage 2017
ISBN: 978-3-319-85497-7
Verlag: Springer International Publishing

Buch, Englisch, 330 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 5212 g

This book describes the current state of the art in big-data analytics, from a technology and hardware architecture perspective. The presentation is designed to be accessible to a broad audience, with general knowledge of hardware design and some interest in big-data analytics. Coverage includes emerging technology and devices for data-analytics, circuit design for data-analytics, and architecture and algorithms to support data-analytics. Readers will benefit from the realistic context used by the authors, which demonstrates what works, what doesn’t work, and what are the fundamental problems, solutions, upcoming challenges and opportunities.

- Provides a single-source reference to hardware architectures for big-data analytics;

- Covers various levels of big-data analytics hardware design abstraction and flow, from device, to circuits and systems;

- Demonstrates how non-volatile memory (NVM) based hardware platforms can be a viable solution to existing challenges in hardware architecture for big-data analytics.

Zielgruppe

Research

Autoren/Hrsg.

Chattopadhyay, Anupam

Yu, Hao

Chang, Chip Hong

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur
• Mathematik | Informatik EDV | Informatik Angewandte Informatik Wirtschaftsinformatik
• Mathematik | Informatik EDV | Informatik Technische Informatik Hochleistungsrechnen, Supercomputer
• Wirtschaftswissenschaften Betriebswirtschaft Wirtschaftsinformatik, SAP, IT-Management

Inhaltsverzeichnis

Part I State-of-the-Art Architectures and Automation for Data-analytics.- Chapter 1. Scaling the Java Virtual Machine on a Many-core System.- Chapter 2.Scaling the Java Virtual Machine on a Many-core System.- Chapter 3.Least-squares based Machine Learning Accelerator for Big-data Analytics in Smart Buildings.- Chapter 4.Compute-in-memory Architecture for Data-Intensive Kernels.- Chapter 5. New Solutions for Cross-Layer System-Level and High-Level Synthesis.- Part II New Solutions for Cross-Layer System-Level and High-Level Synthesis.- Chapter 6.Side Channel Attacks and Efficient Countermeasures on Residue Number System Multipliers.- Chapter 7. Ultra-Low-Power Biomedical Circuit Design and Optimization: Catching The Don’t Cares.- Chapter 8.Acceleration of MapReduce Framework on a Multicore Processor.- Chapter 9. Adaptive dynamic range compression for improving envelope-based speech perception: Implications for cochlear implants.- Part III Emerging Technology, Circuits and Systems for Data-analytics.- Chapter 10. Emerging Technology, Circuits and Systems for Data-analytics.- Chapter 11. Energy Efficient Spiking Neural Network Design with RRAM Devices.- Chapter 12. Efficient Neuromorphic Systems and Emerging Technologies - Prospects and Perspectives.- Chapter 13. In-memory Data Compression Using ReRAMs.- Chapter 14. In-memory Data Compression Using ReRAMs.- Chapter 15.Data Analytics in Quantum Paradigm – An Introduction.

Über Autor(innen)

Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2002 and 2008 respectively. From 2008 to 2009, he worked as a Member of Consulting Staff in CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group in RWTH Aachen, Germany as a Junior Professor. Since September, 2014, he is appointed as an assistant Professor in SCE, NTU. During his PhD, he worked on automatic RTL generation from the architecture description language LISA, which was commercialized later by a leading EDA vendor. He developed several high-level optimizations and verification flow for embedded processors. In his doctoral thesis, he proposed a language-based modeling, exploration and implementation framework for partially re-configurable processors. Together with his doctoral students, he proposed domain-specific high-level synthesis for cryptography, high-level reliabilityestimation flows, generalization of classic linear algebra kernels and a novel multi-layered coarse-grained reconfigurable architecture. In these areas, he published as a (co)-author over 80 conference/ journal papers, several book-chapters and a book. Anupam served in several TPCs of top conferences, regularly reviews journal/ conference articles and presented multiple invited seminars/tutorials in prestigious venues. He is a member of ACM and a senior member of IEEE.

Chang Chip Hong received his B.Eng. (Hons) from National University of Singapore in 1989, and his M.Eng. and Ph.D. from the School of Electrical and Electronic Engineering of Nanyang Technological University, Singapore in 1993 and 1998, respectively. Since 1999, he has been with the School of Electrical and Electronic Engineering, Nanyang Technological University where he is currently an Associate Professor. He holds concurrent appointments at the university as the Assistant Chair (Alumni) of the School of EEE since June 2008, Deputy Director of the Centre for High Performance Embedded Systems (CHiPES) since 2000, and the Program Director of the VLSI Design and Embedded Systems research group of the Centre for Integrated Circuits and Systems (CICS) since 2003. He has published three book chapters and more than 140 refereed international journal and conference papers. He is an Associate Editor of the IEEE Transactions on Circuits and Systems I: Regular Papers from 2010-2011, an Editorial Advisory Board Member of the Open Electrical and Electronic Engineering Journal since 2007, an Editorial Board Member of the Journal of Electrical and Computer Engineering since 2008, and a technical reviewer for several prestigious international journals. He is appointed the Charter Fellow of Advisory Directorate International by the American Biographical Institute, Inc. (ABI) and listed in the Marquis Who's Who in the World since 2008. He is a Senior Member of the IEEE and a Fellow of IET.

Hao Yu obtainedhis B.S. degree from Fudan University (Shanghai China) in 1999, with 4-year first-prize Guanghua scholarship (top-2) and 1-year Samsung scholarship for the outstanding student in science and engineering (top-1). After selected by mini-cuspea program, he spent some time in New York University, and obtained M.S/Ph. D degrees both from electrical engineering department at UCLA in 2007, with major of integrated circuit and embedded computing. He was a senior research staff at Berkeley Design Automation (BDA) since 2006, one of top-100 start-ups selected by Red-herrings at Silicon Valley. Since October 2009, he is an assistant professor at school of electrical and electronic engineering, and also as area director of VIRTUS/VALENS Centre of Excellence, Nanyang Technological University (NTU), Singapore.