Buch, Englisch, 410 Seiten, Paperback, Format (B × H): 155 mm x 235 mm, Gewicht: 7151 g
ISBN: 978-1-4939-5511-4
Verlag: Springer
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
- Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Netzwerkprogrammierung
- Mathematik | Informatik EDV | Informatik Technische Informatik Eingebettete Systeme
- Mathematik | Informatik EDV | Informatik Computerkommunikation & -vernetzung Netzwerkprotokolle
- Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Algorithmen & Datenstrukturen
Weitere Infos & Material
Part I Performance Improvement.- Basic Concepts on On-Chip Networks.- A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs.- Run-Time Deadlock Detection.- The Abacus Turn Model.- Learning-based Routing Algorithms for on-Chip Networks.- Part II Multicast Communication.- Efficient and Deadlock-Free Tree-based Multicast Routing Method for Network-on-Chip.- Path-based Multicast Routing for 2D and 3D Mesh Networks.- Part III Fault Tolerance and Reliability.- Fault-Tolerant Routing Algorithms in Networks-on-Chip.- Reliable and Adaptive Algorithms for 2D and 3D Networks-on-Chip.