Buch, Englisch, 141 Seiten, HC runder Rücken kaschiert, Format (B × H): 160 mm x 241 mm, Gewicht: 3731 g
Buch, Englisch, 141 Seiten, HC runder Rücken kaschiert, Format (B × H): 160 mm x 241 mm, Gewicht: 3731 g
ISBN: 978-3-319-25764-8
Verlag: Springer International Publishing
This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
- Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
- Mathematik | Informatik EDV | Informatik Technische Informatik Eingebettete Systeme
- Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur
- Mathematik | Informatik EDV | Informatik Computerkommunikation & -vernetzung Netzwerkprotokolle
Weitere Infos & Material
Introduction.- Network On Chip Aspects.- Interconnection.- Process Variation.- Synchronous And Asynchronous NoC Design Under High Process Variation.- Novel Routing Algorithm.- Simulation Results.- Conclusions.