Transistor Level Modeling for Analog/RF IC Design

2006. Auflage 2006
ISBN: 978-1-4020-4555-4
Verlag: Springer

Buch, Englisch, 294 Seiten, Format (B × H): 169 mm x 249 mm, Gewicht: 1340 g

This comprehensive volume presents a wealth of practical knowledge in the field of MOS transistor modeling. Coverage includes the 2/3D process and device simulations with a focus on high-voltage MOSFET devices, the development of both PSP and EKV models, and comparisons of physics-based MOSFET models with measurement-based models. The variety of subjects and the high quality content of this volume make it a preferred reference for researchers and users of MOSFET devices and models. The book is recommended for everyone involved in compact model developments, numerical TCAD modeling, parameter extraction, space-level simulation or model standardization.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Grabinski, Wladyslaw

Nauwelaers, Bart

Schreurs, Dominique

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Technische Wissenschaften Sonstige Technologien | Angewandte Technik Angewandte Optik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikrowellentechnik
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Geisteswissenschaften Design Produktdesign, Industriedesign

Inhaltsverzeichnis

2/3-D process and device simulation. An effective tool for better understanding of internal behavior of semiconductor structures.- PSP: An advanced surface-potential-based MOSFET model.- EKV3.0: An advanced charge based MOS transistor model.A design-oriented MOS transistor compact model.- Modelling using high-frequency measurements.- Empirical FET models.- Modeling the SOI MOSFET nonlinearities. An empirical approach.- Circuit level RF modeling and design.- On incorporating parasitic quantum effects in classical circuit simulations.- Compact modeling of the MOSFET in VHDL-AMS.- Compact modeling in Verilog-A.

Über Autor(innen)

Dr. Grabinski, Dr. Nauwelaers and Dr. Scheurs organized the MOS-Modeling workshop at the European Solid-State Devices Conference (ESSDERC) in 2004, and due to popular request will do again at ESSDERC 2005 in Grenoble. Dr. Grabinski is in industry, at Freescale Semiconductor, while Dr. Nauwelaers and Dr. Schreurs are in academia.