Buch, Englisch, 318 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 670 g
Buch, Englisch, 318 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 670 g
Reihe: Integrated Circuits and Systems
ISBN: 978-0-387-36641-8
Verlag: Springer US
A project’s functional verification testplan is the specification for the verification process. Developing this testplan usually involves the entire engineering team (architects, designers, and verification engineers). This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. This is the first book published on this subject. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions. Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP.
Zielgruppe
Professional/practitioner
Autoren/Hrsg.
Fachgebiete
- Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
- Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie
- Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
- Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
- Geisteswissenschaften Design Produktdesign, Industriedesign
- Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
- Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
Weitere Infos & Material
Definitions and Terminology.- The Process.- Bus-Based Design Example.- Interfaces.- Arbiters.- Controllers.- Datapath.
