Variation Tolerant On-Chip Interconnects

2012
ISBN: 978-1-4614-0130-8
Verlag: Springer

Buch, Englisch, 172 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 448 g

Reihe: Analog Circuits and Signal Processing

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.

Zielgruppe

Research

Autoren/Hrsg.

Nigussie, Ethiopia Enideg

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren

Inhaltsverzeichnis

Introduction.- On-Chip Communication.- Interconnect Design Techniques.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.

Über Autor(innen)

Introduction.- Interconnect Design Techniques.- On-Chip Wire Modeling.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.