Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

2. Auflage Softcover version of original hardcover Auflage 2007
ISBN: 978-1-4419-4285-2
Verlag: Springer US

Buch, Englisch, Band 34, 328 Seiten, Paperback, Format (B × H): 155 mm x 235 mm, Gewicht: 534 g

Reihe: Frontiers in Electronic Testing

This book is essential to understand new test methodologies, algorithms and industrial practices. Without its insight into the physics of nano-metric technologies, it would be difficult to develop system-level test strategies that yield a high IC fault coverage. The work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. The 2nd edition of Defect Oriented Testing has been extensively updated with the addition of chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering to provide a link between defect sources and yield. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Pineda de Gyvez, José

Sachdev, Manoj

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Functional and Parametric Defect Models.- Digital CMOS Fault Modeling.- Defects in Logic Circuits and their Test Implications.- Testing Defects and Parametric Variations in RAMs.- Defect-Oriented Analog Testing.- Yield Engineering.- Conclusion.