Buch, Englisch, 67 Seiten, Paperback, Format (B × H): 187 mm x 235 mm
Buch, Englisch, 67 Seiten, Paperback, Format (B × H): 187 mm x 235 mm
Reihe: Synthesis Lectures on Computer Architecture
ISBN: 978-1-60845-952-0
Verlag: MORGAN & CLAYPOOL
To overcome the memory wall, designers have resorted to a hierarchy of cache memory levels, which rely on the principal of memory access locality to reduce the observed memory access time and the performance gap between processors and memory. Unfortunately, important workload classes exhibit adverse memory access patterns that baffle the simple policies built into modern cache hierarchies to move instructions and data across cache levels. As such, processors often spend much time idling upon a demand fetch of memory blocks that miss in higher cache levels. Prefetching—predicting future memory accesses and issuing requests for the corresponding memory blocks in advance of explicit accesses—is an effective approach to hide memory access latency. There have been a myriad of proposed prefetching techniques, and nearly every modern processor includes some hardware prefetching mechanisms targeting simple and regular memory access patterns. This primer offers an overview of the various classes of hardware prefetchers for instructions and data proposed in the research literature, and presents examples of techniques incorporated into modern microprocessors.
Autoren/Hrsg.
Weitere Infos & Material
- Preface
- Introduction
- Instruction Prefetching
- Data Prefetching
- Concluding Remarks
- Bibliography
- Author Biographies