System-On-A-Chip Verification

Methodology and Techniques
2002. Auflage 2000
ISBN: 978-0-7923-7279-0
Verlag: Springer Us

Buch, Englisch, 372 Seiten, Format (B × H): 165 mm x 244 mm, Gewicht: 771 g

is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for application.
takes a systematic approach that covers the following aspects of verification strategy in each chapter:

1. Explanation of the objective involved in performing verification after a given design step;
2. Features of options available;
3. When to use a particular option;
4. How to select an option; and
5. Limitations of the option.

This exciting new book will be of interest to all designers and test professionals.

Zielgruppe

Research

Autoren/Hrsg.

Rashinkar, Prakash

Paterson, Peter

Singh, Leena

Fachgebiete

• Mathematik | Informatik EDV | Informatik Technische Informatik Systemverwaltung & Management
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Mathematik | Informatik EDV | Informatik Informatik
• Geisteswissenschaften Design Produktdesign, Industriedesign

Inhaltsverzeichnis

System-level Verification.- Block-level Verification.- Analog/Mixed Signal Simulation.- Simulation.- Hardware/Software Co-verification.- Static Netlist Verification.- Physical Verification and Design Sign-off.