Timing Analysis and Optimization of Sequential Circuits

1999
ISBN: 978-1-4613-7579-1
Verlag: Springer US

Buch, Englisch, 190 Seiten, Paperback, Format (B × H): 155 mm x 235 mm, Gewicht: 330 g

Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems.
describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in timing analysis and optimization techniques is described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques: retiming and clock skew optimization.
covers the following topics:

• Algorithms for sequential timing analysis
• Fast algorithms for clock skew optimization and their applications
• Efficient techniques for retiming large sequential circuits
• Coupling sequential and combinational optimizations.

is written for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design.

Zielgruppe

Research

Autoren/Hrsg.

Sapatnekar, S.

Maheshwari, Naresh

Fachgebiete

• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Energietechnik | Elektrotechnik Elektrotechnik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

1. Introduction.- 1.1 Performance Optimization of VLSI Circuits.- 1.2 Outline of the Book.- 2. Timing Analysis of Sequential Circuits.- 2.1 Introduction.- 2.2 Combinational Delay Modeling.- 2.3 Clocking Disciplines: Edge-Triggered Circuits.- 2.4 Resolving Short Path Violations.- 2.5 Clocking Disciplines: Level-clocked Circuits.- 2.6 Clock Schedule Optimization for Level-Clocked Circuits.- 2.7 Timing Analysis of Domino Logic.- 2.8 Concluding Remarks.- 3. Clock Skew Optimization.- 3.1 The Notion of Deliberate Clock Skew.- 3.2 Is Clock Skew Optimization Safe?.- 3.3 Clock Tree Construction.- 3.4 Clock Skew Optimization.- 3.5 Clock Skew Optimization with Transistor Sizing.- 3.6 Wave Pipelining Issues.- 3.7 Deliberate Skews for Peak Current Reduction.- 3.8 Conclusion.- 4. The Basics of Retiming.- 4.1 Introduction to Retiming.- 4.2 A Broad Overview of Research on Retiming.- 4.3 Modeling and Assumptions for Retiming.- 4.4 Minperiod Optimization of Edge-triggered Circuits.- 4.5 Level-clocked Circuits.- 4.6 Concluding Remarks.- 5. Minarea Retiming.- 5.1 The Leiserson-Saxe Approach.- 5.2 The Minaret Algorithm.- 5.3 Minarea Retiming of Level-Clocked Circuits.- 6. Retiming Control Logic.- 6.1 Minperiod Initial State Retiming via the State Transition Graph.- 6.2 Minperiod Initial State Retiming via Reverse Retiming.- 6.3 Minarea Initial State Retiming.- 6.4 Maintaining Initial States With Explicit Reset Circuitry.- 7. Miscellaneous Issues in Retiming.- 7.1 Retiming and Testing.- 7.2 Verification Issues.- 7.3 Retiming for Low Power.- 7.4 Retiming with Logic Synthesis.- 7.5 Retiming for FPGA’s.- 7.6 Practical Issues.- 7.7 Conclusion.- 8. Conclusion.- References.