Serpanos / Wolf Architecture of Network Systems

1. Auflage 2011
ISBN: 978-0-08-092282-9
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: 6 - ePub Watermark

E-Book, Englisch, 344 Seiten

Reihe: The Morgan Kaufmann Series in Computer Architecture and Design

Architecture of Network Systems explains the practice and methodologies that will allow you to solve a broad range of problems in system design, including problems related to security, quality of service, performance, manageability, and more. Leading researchers Dimitrios Serpanos and Tilman Wolf develop architectures for all network sub-systems, bridging the gap between operation and VLSI.This book provides comprehensive coverage of the technical aspects of network systems, including system-on-chip technologies, embedded protocol processing and high-performance, and low-power design. It develops a functional approach to network system architecture based on the OSI reference model, which is useful for practitioners at every level. It also covers both fundamentals and the latest developments in network systems architecture, including network-on-chip, network processors, algorithms for lookup and classification, and network systems for the next-generation Internet.The book is recommended for practicing engineers designing the architecture of network systems and graduate students in computer engineering and computer science studying network system design. - This is the first book to provide comprehensive coverage of the technical aspects of network systems, including processing systems, hardware technologies, memory managers, software routers, and more - Develops a systematic approach to network architectures, based on the OSI reference model, that is useful for practitioners at every level - Covers both the important basics and cutting-edge topics in network systems architecture, including Quality of Service and Security for mobile, real-time P2P services, Low-Power Requirements for Mobile Systems, and next generation Internet systems

Dimitrios Serpanos is a Professor of Computer Architecture at the Department of Electrical and Computer of the University of Patras in Patras, Greece. He is also Director-elect of the Industrial Systems Institute (ISI) in Patras. Professor Serpanos holds a PhD in Computer Science from Princeton University (1990), an MA in Computer Science from Princeton (1988) and a Diploma in Computer Engineering and Informatics from the University of Patras (1985). Before joining the University of Patras, Professor Serpanos was a Professor (Assistant at first and Associate later) at the Department of Computer Science, University of Crete, Greece (1996-2000) and earlier, he was a Research Staff Member at IBM T.J. Watson Research Center, New York, USA. In addition to his faculty appointments, he has also been conducting research at research institutes, specifically ICS-FORTH, while in Crete, and ISI while in Patras. Professor Serpanos has been a leader in the area of architecture of network systems, working on such systems for almost 20 years. He introduced the concept of specialized protocol processors (1992) and authored the first paper on multi-protocol, multiprocessor router architectures (1994). He has written more than 100 research papers in high quality conferences and research journals, addressing architectures and design issues of all types of network systems, from switches to routers and gateways. He has also worked on Quality-of-Service issues and has extensive activity in network and computer security. In addition to his research papers, Professor Serpanos holds 2 US patents and 7 invention disclosures in the area of network systems. Professor Serpanos has received awards and distinctions as a graduate student, an IBM employee and as a faculty (2005 IBM Faculty Award). Furthermore, he is the General Chair of 2 IEEE Conferences, Technical Program Chair in 2 IEEE Conferences, organizer (twice) of an ACM Workshop, member of Technical Program Committees for conferences and workshops (over 25) and panel organizer for several conferences. He has served also in additional positions in conference organizing committees. In relevance to the subject of the book, Professor Serpanos is the leading Guest-Editor of a special issue of IEEE Network on Advances in Network Systems Architecture and the organizer and coordinator of a Task Force on Network Systems Architecture in the E-NEXT European Network of Excellence. Professor Serpanos is a Senior Member of the IEEE; a member of ACM, IET, NYAS, and the Technical Chamber of Greece; he is also an educational member of USENIX.

Autoren/Hrsg.

Serpanos, Dimitrios

Wolf, Tilman

Inhaltsverzeichnis

1;Front Cover;1
2;Architecture of Network Systems;4
3;Copyright;5
4;Dedication;6
5;Contents;8
6;Preface;14
6.1;Why write this book?;14
6.2;Target audience;14
6.3;Approach;14
6.4;Course use;15
6.5;We want to hear from you;15
6.6;Acknowledgments;16
7;About the Authors;18
8;Chapter 1: Architecture of network systems overview;20
8.1;Computer networks;20
8.2;Embedded systems;22
8.3;Protocols and network systems;24
8.4;Organization of this book;25
9;Chapter 2: Network protocols and network systems;30
9.1;Introduction;30
9.2;The open systems interconnection reference model;31
9.3;Protocol stacks and protocol elements;32
9.4;Network systems: definition and types;36
9.5;Structure of network systems;40
9.6;Summary;43
10;Chapter 3: Requirements of network systems;44
10.1;Introduction;44
10.2;Requirements of network applications and services;45
10.2.1;Qualitative requirements;46
10.2.2;Quantitative requirements;46
10.2.3;Example requirements;47
10.3;The throughput preservation challenge;48
10.4;Traffic models and benchmarks;51
10.5;Summary;52
11;Chapter 4: Interconnects and switching fabrics;54
11.1;Introduction;54
11.2;Crossbars and interconnection networks;57
11.3;Switch organization;59
11.4;Switch scheduling;62
11.4.1;Centralized scheduling;65
11.4.2;Distributed scheduling;68
11.4.3;Use of randomization;76
11.4.4;Real-time traffic;80
11.5;Summary;80
12;Chapter 5: Network adapters;82
12.1;Introduction;82
12.2;Basic network adapter;83
12.3;Adapter operation analysis;85
12.4;Memory organization;89
12.4.1;Memory management unit with local memory;89
12.4.2;Memory management unit and processor with local memory;92
12.5;Intelligent DMA;94
12.6;Multiprocessor processing element;96
12.6.1;Single SPE configuration;98
12.6.2;Multi-SPE configuration—protocol multiprocessing;99
12.6.3;Multi-SPE configuration—spatial parallelism;100
12.7;Memory management schemes;103
12.7.1;Detached MMU;105
12.7.2;Distributed MMUs;106
12.8;Summary;106
13;Chapter 6: Bridges and layer 2 switches;108
13.1;Introduction;108
13.2;Types of bridges;110
13.3;Transparent bridging and special-purpose subsystems;111
13.4;High-performance transparent bridge architecture;116
13.4.1;Transparent bridging support unit;120
13.4.2;Network attachment unit design;123
13.4.3;lnternal switching component operation;126
13.4.4;Partitioned data memory organization;128
13.4.5;Layer 2 switches;129
13.5;Summary;129
14;Chapter 7: Routers;130
14.1;Network layer;130
14.1.1;Functionality of the network layer;130
14.1.2;Systems requirements;131
14.1.3;Generic router design;134
14.2;Data plane;136
14.2.1;Route lookup;137
14.2.2;Queuing and buffering management;145
14.3;Control plane;148
14.3.1;Routing algorithms;148
14.3.2;Error handling;155
14.4;Example network layer systems;158
14.5;Summary;159
15;Chapter 8: Transport layer systems;160
15.1;Transport layer;160
15.1.1;Functionality of the transport layer;160
15.1.2;Network flows;162
15.1.3;Packet classification;166
15.1.4;Transport layer systems;175
15.2;Summary;179
16;Chapter 9: Application layer systems;180
16.1;Application layer;180
16.1.1;Functionality of the application layer;181
16.1.2;Application layer protocols;182
16.2;Network system support for application layer;191
16.2.1;Payload inspection;191
16.2.2;Load balancing;199
16.3;Summary;201
17;Chapter 10: Quality of service and security;202
17.1;Cross-layer issues;202
17.2;Quality of service;202
17.2.1;Quality of service concepts;203
17.2.2;Network support for QoS;206
17.2.3;Link scheduling algorithms;207
17.2.4;Quality of service summary;218
17.3;Security;218
17.3.1;Security concepts;218
17.3.2;Cryptography overview;219
17.3.3;Security in network protocols;223
17.3.4;Denial-of-service attacks;226
17.4;Summary;229
18;Chapter 11: Specialized hardware components;230
18.1;Hardware support for packet forwarding;230
18.2;General-purpose packet processors;230
18.2.1;Performance vs flexibility;231
18.2.2;Systems-on-a-chip;232
18.2.3;Network processors;233
18.2.4;Design choices;239
18.2.5;Example systems;242
18.3;Special-purpose hardware accelerators;243
18.3.1;Trade-offs in use of accelerators;243
18.3.2;Example accelerators;244
18.3.3;Accelerator implementations;245
18.4;Summary;246
19;Chapter 12: Power issues in network systems;248
19.1;Introduction;248
19.2;Lookup engines;249
19.3;Network processors;254
19.4;Summary;256
20;Chapter 13: Networks on chips;258
20.1;Introduction;258
20.2;Network-on-chip architectures;259
20.3;Network-on-chip routing schemes;260
20.4;Technology and circuit design;261
20.4.1;Bus delay model;262
20.4.2;Crossbar delay model;263
20.4.3;Power issues;266
20.5;Summary;267
21;Chapter 14: Run-time support systems;268
21.1;Software support for network systems;268
21.1.1;Network dynamics;269
21.1.2;Run-time components;269
21.1.3;Software interfaces;271
21.2;Operating system support for networking;272
21.2.1;Networking software in operating systems;272
21.2.2;Software interactions;273
21.2.3;Performance considerations;275
21.3;Specialized router software;278
21.3.1;Router operating systems;278
21.3.2;Packet processing software;281
21.4;Summary;284
22;Chapter 15: Next-generation Internet architecture;286
22.1;Need for next-generation internet;286
22.2;Networking trends;286
22.2.1;Limitations in the Internet;287
22.2.2;Extended reach of the Internet;288
22.2.3;New networking paradigms;289
22.2.4;Implications;292
22.3;Network virtualization;292
22.3.1;Diversity of protocols;292
22.3.2;Single infrastructure;293
22.3.3;Virtualized networks;294
22.4;Programmability;296
22.4.1;Programmability in next-generation networks;296
22.4.2;Implementing programmability;298
22.4.3;Experimental testbeds;299
22.4.4;Commercial incentives;300
22.5;Summary;300
23;Appendix: The layered Internet architecture and network protocols;302
23.1;Layered internet architecture;302
23.1.1;Hourglass architecture;303
23.1.2;Protocol processing in network systems;304
23.1.3;Example protocol stack;305
23.1.4;Link layer;306
23.1.5;Medium access control;306
23.1.6;Ethernet;309
23.2;Network layer;311
23.2.1;Internet protocol suite;311
23.2.2;Internet protocol;311
23.3;Transport layer;313
23.3.1;Reliable data transfer;314
23.3.2;Transmission control protocol;316
23.4;Summary;318
24;References;320
25;Index;332