Payvadosi, Navid
Navid Paydavosi is a seasoned hardware engineer with a decade of experience in advanced Si process technology and GPU and memory subsystem optimization. He excels in optimizing PPAC for complex SoC systems. He holds a Ph.D. in Electrical Engineering from the University of Alberta and completed a postdoctoral scholarship at UC Berkeley under supervision of Prof. Chenming Hu, contributing to the development of FinFET and SOI SPICE compact models. Navid began his Intel career in 2014 as a Logic Technology Development Device Engineer, where he contributed to key advancements in Intel 4 and Intel 3 technology nodes. He then served as a GPU Micro-Arch Power Optimization Engineer, leading innovations such as a novel Glitch minimization algorithm. As a NAND Flash Power and Performance Optimization Engineer, Navid significantly improved the power and performance of Intel's 3D NAND Flash products. Currently, he is a Senior Staff Intel Foundry Device Engineer, customizing the Intel 3 technology node for customers. Navid's expertise spans device physics, semiconductor manufacturing, and power optimization. His goal is to deliver world-class AI hardware solutions for Data Center and Edge computing environments.
Duarte, Juan Pablo
Juan Pablo Duarte Sepúlveda obtained his Ph.D. at the University of California, Berkeley in 2018. He received his B.Sc. in 2010 and his M.Sc. in 2012, both in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST). He held a position as a lecturer at the Universidad Tecnica Federico Santa Maria, Valparaiso, Chile, in 2012. He has authored many papers on nanoscale semiconductor device modeling and characterization. He received the Best Student Paper Award at the 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) for the paper: Unified FinFET Compact Model: Modelling Trapezoidal Triple-Gate FinFETs.
Hu, Chenming
Chenming Hu is TSMC Distinguished Chair Professor Emeritus at the University of California, Berkeley. He was the Chief Technology Officer of TSMC. He received the US Presidential Medal of Technology and Innovation from Pres. Barack Obama for developing the first 3D thin-body transistor FinFET, MOSFET reliability models and leading the development of BSIM industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica.He received the highest honor of IEEE, the IEEE Medal of Honor, and its Andrew Grove Award, Solid Circuits Award, and the Nishizawa Medal. He also received the Taiwan Presidential Science Prize and UC Berkeley's highest honor for teaching - the Berkeley Distinguished Teaching Award.
Lu, Darsen
Darsen D. Lu was one of the key contributors of the industry standard FinFET compact model, BSIM-CMG, and thin-body SOI compact model, BSIM-IMG. He received his B.Sc. in electrical engineering in 2005, from National Tsing Hua University, Hsinchu, Taiwan, and his M.Sc. and Ph.D. in electrical engineering from the University of California, Berkeley, in 2007 and 2011 respectively. From 2011 to 2015, he has been a research scientist at the IBM Thomas J. Watson Research Center, Yorktown Heights, New York. He is currently a Macronix Endowed Chair (Associate) Professor at National Cheng Kung University, Tainan, Taiwan. His current research focuses on the fabrication and modeling of ferroelectric memory (ferroelectric FinFET) devices, cryogenic CMOS modeling for high-performance and quantum computation, and the design of AI/neuromorphic circuits and systems.
Khandelwal, Sourabh
Sourabh Khandelwal is an Associate Professor at Macquarie University. He is the lead author of two industry standard compact models: ASM-HEMT for GaN RF and power technology, and ASM-ESD for silicon ESD applications. He has also co-authored BSIM-CMG, BSIM-IMG and BSIM6 compact models during his tenure at the BSIM group at the University of California Berkeley. Dr Khandelwal has published 3 books and over 150 research papers. He regularly serves as consultant to multi-national semiconductor companies.
Vanugopalan, Sriramkumar
Sriramkumar Venugopalan received his M.Sc. and Ph.D. in electrical engineering at the University of California, Berkeley and his B.Sc. from the Indian Institute of Technology (IIT), Kanpur. While pursuing his doctoral degree he contributed to research and development of multi-gate transistor compact SPICE models. He lead the industry standardization effort for BSIM-CMG model representing the BSIM Group at the Compact Model Council. He was the recipient of Outstanding Researcher Award from TSMC for his contributions to multi-gate SPICE models. He has authored and co- authored more than 30 research papers in the area of semiconductor device SPICE models and RF integrated circuit design. Dr. Venugopalan is currently leading wireless system design group at Skyworks Solutions, Inc. Prior to that he co-founded and was the CEO of RF Pixels, a 5G mmWave Radio startup which was later acquired by Skyworks. Dr. Venugopalan was also with Samsung Electronics pursuing RF integrated circuit design in advanced semiconductor technology nodes.
Chauhan, Yogesh Singh
Yogesh Singh Chauhan is a Chair professor in the department of electrical engineering at Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices. He is the Fellow of IEEE and Indian National Academy of Engineering. He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the chairperson of IEEE U.P. section and IEEE-EDS Compact Modeling Committee. He has published more than 400 papers in international journals and conferences. He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award, Humboldt fellowship and Swarnajayanti fellowship in 2018. He has served in the technical program committees of IEEE International Electron Devices Meeting (IEDM), IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE European Solid-State Device Research Conference (ESSDERC), IEEE Electron Devices Technology and Manufacturing (EDTM), and IEEE International Conference on VLSI Design and International Conference on Embedded Systems.
