Siddiqi Dynamic RAM

Technology Advancements
1. Auflage 2012
ISBN: 978-1-4398-9375-3
Verlag: CRC Press
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 382 Seiten

Because of their widespread use in mainframes, PCs, and mobile audio and video devices, DRAMs are being manufactured in ever increasing volume, both in stand-alone and in embedded form as part of a system on chip. Due to the optimum design of their components—access transistor, storage capacitor, and peripherals—DRAMs are the cheapest and densest semiconductor memory currently available. As a result, most of DRAM structure research and development focuses on the technology used for its constituent components and their interconnections. However, only a few books are available on semiconductor memories in general and fewer on DRAMs.
Dynamic RAM: Technology Advancements provides a holistic view of the DRAM technology with a systematic description of the advancements in the field since the 1970s, and an analysis of future challenges.
Topics Include:

- DRAM cells of all types, including planar, three-dimensional (3-D) trench or stacked, COB or CUB, vertical, and mechanically robust cells using advanced transistors and storage capacitors

- Advancements in transistor technology for the RCAT, SCAT, FinFET, BT FinFET, Saddle and advanced recess type, and storage capacitor realizations

- How sub 100 nm trench DRAM technologies and sub 50 nm stacked DRAM technologies and related topics may lead to new research

- Various types of leakages and power consumption reduction methods in active and sleep mode

- Various types of SAs and yield enhancement techniques employing ECC and redundancy

A worthwhile addition to semiconductor memory research, academicians and researchers interested in the design and optimization of high-density and cost-efficient DRAMs may also find it useful as part of a graduate-level course.

Zielgruppe

Electrical/electronics engineers, semiconductor circuit designers, chemical/mechanical engineers, semiconductor process development engineers, and circuit designers; senior undergraduate and graduate students studying digital circuit design.

Autoren/Hrsg.

Siddiqi, Muzaffer A.

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Random Access Memories
Static Random Access Memory
Dynamic Random Access Memories: Basics
One-Transistor DRAM Cell
Initial-Stage DRAM Technology Developments
DRAM Operating Modes
Silicon-on-Insulator Technology Based DRAMs
Advanced Nonvolatile Memories

DRAM Cell Development
Planar DRAM Cell
Three-Dimensional Capacitor DRAM Cell
Access Transistor Stacked above the Trench Capacitor Cell
Trench Transistor Cell
Buried Storage Electrode Cell
Buried Capacitor or Stacked Transistor Cell
Stacked Capacitor Cells

DRAM Technologies
DRAM Technology—Early Stage Development
Two-Dimensional DRAM Cell
16 Mbit–256 Mbit, 1 Gbit DRAM Development
Capacitor over Bit Line (COB) DRAM Cell

Advanced DRAM Cell Transistors
Recess-Channel- Array Transistor
Vertical Depleted Lean-Channel Transistor Structure
FinFET—A Self-Aligned DG-MOSFET
Body Tied MOSFETs/Bulk FinFETs
Multichannel FET
Saddle MOSFET
Saddle-Fin FET
Surrounding Gate Transistor
Three-Dimensional Memory Architecture: Cell Area Less Than 4 F2
BEST and VERIBEST DRAM Cells
Vertical Transistors
Advanced Recessed FinFETs

Storage Capacitor Enhancement Techniques
Hemispherical Grain Storage Node
Higher Permittivity and Layered Dielectrics
Low-Temperature HSG
Sub–100 nm Trench Capacitor Drams
Metal Insulator Metal Capacitor Structure

Advanced DRAM Technologies
Advanced Cell Structures
Robust Memory Cell—Mechanical Stability of Storage Node
DRAM Cell Transistor Technology
Cell Capacitor Technology
Lithography Technology
Isolation Techniques
Bit Line, Word Line, and Gate Technology
Cell Connections
Interconnection/Metallization Technology
Advanced DRAM Technology Developments
Embedded DRAMs

Leakages in DRAMs
Leakage Currents in DRAMs
Power Dissipation in DRAMs
Cell Signal Charge
Power Dissipation for Data Retention
Low-Power Schemes in DRAM
On-Chip Voltage Converter Circuits
Refresh Time Extension
Subthreshold Current Reduction
Multithreshold-Voltage CMOS Schemes
VGS Reverse Biasing
Leakage Current Reduction Techniques in DRAMs
Analysis of Subthreshold Leakage Reduction
Subthreshold Leakage Reduction for Low-Voltage Applications
Data Retention Time and its Improvement

Memory Peripheral Circuits
Address Decoder Basics
Address Decoding Developments
DRAM Sense Amplifiers
Error Checking and Correction
On Chip Redundancy Techniques and ECC
Redundancy Schemes for High-Density DRAMs