Designing Fast CMOS Circuits
Buch, Englisch, 256 Seiten, Gewicht: 485 g
ISBN: 978-1-55860-557-2
Verlag: Elsevier Science & Technology
The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.
Zielgruppe
This book is intended for anyone who designs CMOS integrated circuits.
Autoren/Hrsg.
Fachgebiete
Weitere Infos & Material
1 The Method of Logical Effort2 Design Examples3 Deriving the Method of Logical Effort4 Calculating the Logical Effort of Gates5 Calibrating the Model6 Asymmetric Logic Gates7 Unequal Rising and Falling Delays8 Circuit Families9 Forks of Amplifiers10 Branches and Interconnect11 Wide Structures12 ConclusionsA Cast of CharactersB Reference process parametersC Logical Effort ToolsD Solutions