Ielmini / Waser Resistive Switching

From Fundamentals of Nanoionic Redox Processes to Memristive Device Applications
1. Auflage 2015
ISBN: 978-3-527-68094-8
Verlag: Wiley-VCH
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 755 Seiten, E-Book

Dieses umfassende und wertvolle Referenzwerk führt die Leser in dieses breit gefächerte Fachgebiet ein, vermittelt das notwendige Wissen, Werkzeuge und Methoden, um Speicher mit resistiver Schaltung zu verstehen, zu charakterisieren und einzusetzen.

Autoren/Hrsg.

Ielmini, Daniele

Waser, Rainer

Inhaltsverzeichnis

INTRODUCTION

 

TRANSITION METAL OXIDES

Atomic Structures of Selected Binary, Ternary Oxides

Deposition Techniques

Thermodynamics of Oxidation, Ellingham Diagram

Electronic Structure and Conduction

Correlated Electrons

Ionic Conduction

 

RESISTIVE SWITCHING

Device Structure

Unipolar Switching: Forming, Set/Reset Operations

Bipolar Switching: Forming, Set/Reset Operations

Coexistence of Unipolar/Bipolar Switching

Filamentary Switching and Atomic Force Microscopy Analysis

Interface Switching

Threshold and Memory Switching

Time Dependence of Set/Reset

Resistance Dependence of Set/Reset

 

SWITCHING MECHANISMS AND MODELS

Unipolar Switching: Set/Reset Mechanisms and Models

Bipolar Switching: Set/Reset Mechanisms and Models

Modeling of Resistance Dependence (Filament Size and Gap)

Modeling of Time Dependence

Modeling of Set Current Dependence

Overshoot and Parasitic Effects

Material Dependence and Universal Switching

 

MEMORY RELIABILITY

Read Disturb and The Time-Voltage Dilemma

Data Retention

1/f and Random Telegraph Signal Noise

Switching Variability and Set/Reset Algorithms

Reset Current Reduction

Set/Reset Instability

Cycling Endurance

 

MEMORY CELL STRUCTURES

MIM Structures

Bilayered Structures

Lighting-Rod Structures

Contact RRAM

Complementary Resistance Switch (CRS)

Multilevel Cells

Alternative Materials: OxRRAM, PoRRAM, CBRAM

Bottom-Up Approaches: Nanotubes, Nanowires and Self-Assembly

 

MEMORY ARCHITECTURES

Crossbar Array

Diode Selectors

Transistor Selectors

1T1R Architectures

CMOL

Scaling Issues (Series Resistance, Programming Cross Talk, 3D Stacking Issues)

 

LOGIC GATES

The Memristor

Crossbar Latch

Data Restoration

IMP Function

STDP in Memristor Gates

 

CONCLUSIONS

INTRODUCTION

 

TRANSITION METAL OXIDES

Atomic Structures of Selected Binary, Ternary Oxides

Deposition Techniques

Thermodynamics of Oxidation, Ellingham Diagram

Electronic Structure and Conduction

Correlated Electrons

Ionic Conduction

 

RESISTIVE SWITCHING

Device Structure

Unipolar Switching: Forming, Set/Reset Operations

Bipolar Switching: Forming, Set/Reset Operations

Coexistence of Unipolar/Bipolar Switching

Filamentary Switching and Atomic Force Microscopy Analysis

Interface Switching

Threshold and Memory Switching

Time Dependence of Set/Reset

Resistance Dependence of Set/Reset

 

SWITCHING MECHANISMS AND MODELS

Unipolar Switching: Set/Reset Mechanisms and Models

Bipolar Switching: Set/Reset Mechanisms and Models

Modeling of Resistance Dependence (Filament Size and Gap)

Modeling of Time Dependence

Modeling of Set Current Dependence

Overshoot and Parasitic Effects

Material Dependence and Universal Switching

 

MEMORY RELIABILITY

Read Disturb and The Time-Voltage Dilemma

Data Retention

1/f and Random Telegraph Signal Noise

Switching Variability and Set/Reset Algorithms

Reset Current Reduction

Set/Reset Instability

Cycling Endurance

 

MEMORY CELL STRUCTURES

MIM Structures

Bilayered Structures

Lighting-Rod Structures

Contact RRAM

Complementary Resistance Switch (CRS)

Multilevel Cells

Alternative Materials: OxRRAM, PoRRAM, CBRAM

Bottom-Up Approaches: Nanotubes, Nanowires and Self-Assembly

 

MEMORY ARCHITECTURES

Crossbar Array

Diode Selectors

Transistor Selectors

1T1R Architectures

CMOL

Scaling Issues (Series Resistance, Programming Cross Talk, 3D Stacking Issues)

 

LOGIC GATES

The Memristor

Crossbar Latch

Data Restoration

IMP Function

STDP in Memristor Gates

 

CONCLUSIONS

Über Autor(innen)

Daniele Ielmini is associate professor in the Department of Electrical Engineering, Information Science and Bioengineering, Politecnico di Milano, Italy. He obtained his Ph.D. in Nuclear Engineering from Politecnico di Milano in 2000. He held visiting positions at Intel and Stanford University in 2006. His research group investigates emerging device technologies, such as phase change memory (PCM) and resistive switching memory (ReRAM) for both memory and computing applications. He has authored six book chapters, more than 200 papers published in international journals and presented at international conferences, and four patents to his name. Professor Ielmini received the Intel Outstanding Research Award in 2013 and the ERC Consolidator Grant in 2014.

 

Rainer Waser is professor at the faculty for Electrical Engineering and Information Technology at the RWTH Aachen University and director at the Peter Grünberg Institute at the Forschungszentrum Jülich (FZJ), Germany. His research group is focused on fundamental aspects of electronic materials and on such integrated devices as nonvolatile memories, logic devices, sensors and actuators.

Professor Waser has published about 500 technical papers. Since 2003, he has been the coordinator of the research program on nanoelectronic systems within the Germany national research centres in the Helmholtz Association. In 2007, he has been co-founder of the Jülich-Aachen Research Alliance, section Fundamentals of Future Information Technology (JARA-FIT). In 2014, he was awarded the Gottfried Wilhelm Leibniz Prize of the Deutsche Forschungsgemeinschaft and the Tsungming Tu Award of the Ministry of Science and Technology of Taiwan.