Ultra Clean Processing of Semiconductor Surfaces IX

Erscheinungsjahr 2009
ISBN: 978-3-908451-64-8
Verlag: Trans Tech Publications

Buch, Englisch, 412 Seiten, Format (B × H): 170 mm x 240 mm, Gewicht: 900 g

Volume is indexed by Thomson Reuters CPCI-S (WoS).The contents of this publication include every conceivable issue related to contamination, cleaning and surface preparation during mainstream large-scale integrated circuit manufacture. Typically, silicon is used as the main semiconductor substrate. However, other semiconducting materials such as SiGe and SiC are currently being used in the source-sink junction areas, and materials such as Ge and III-V compounds are being considered for the transistor channel region of future-generation devices.

Autoren/Hrsg.

Mertens, Paul

Meuris, Marc

Heyns, Marc

Fachgebiete

• Technische Wissenschaften Maschinenbau | Werkstoffkunde Produktionstechnik Industrielle Qualitätskontrolle
• Technische Wissenschaften Maschinenbau | Werkstoffkunde Produktionstechnik Fertigungstechnik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie
• Technische Wissenschaften Maschinenbau | Werkstoffkunde Technische Mechanik | Werkstoffkunde Materialwissenschaft: Elektronik, Optik
• Naturwissenschaften Physik Elektromagnetismus Halbleiter- und Supraleiterphysik
• Technische Wissenschaften Maschinenbau | Werkstoffkunde Produktionstechnik Werkzeugbau

Inhaltsverzeichnis

Acknowledgements
Committees and Sponsors
Photo
Preface
I. Physical Cleaning Methods
Direct Observation of Single Bubble Cavitation Damage for MHz Cleaning
High Speed Imaging of 1 MHz Driven Microbubbles in Contact with a Rigid Wall
Characterization of a Cavitation Bubble Structure at 230 kHz: Bubble Population, Sonoluminescence and Cleaning Potential
Impact of Megasonic Activation with Different Chemistries on Silicon Surface in Single Wafer Tool
Impacts of Ionization Potentials and Megasonic Dispersion
The Influence of Standing Waves on Cleaning with a Megasonic Nozzle
Megasonic Sweeping and Silicon Wafer Cleaning
Removal of Nano-Particles by Aerosol Spray: Effect of Droplet Size and Velocity on Cleaning Performance
High Aspect Ratio Contact Clean Study in 58nm Flash Device
High Velocity Aerosol Cleaning with Organic Solvents: Particle Removal and Substrate Damage
Cleaning Technique Using High-Speed Steam-Water Mixed Spray
Pattern Collapse and Particle Removal Forces of Interest to Semiconductor Fabrication Process
Applications of Electrostatic Spray Techniques to Surface Cleaning
Analyzing the Collapse Force of Narrow Lines Measured by Lateral Force AFM Using an Analytical Mechanical Model
II. Particle Interactions
Reduced Particle Removal Efficiency Upon Wafer Storage
Local Distribution of Particles Deposited on Patterned Surfaces
Particle Retention Mechanism of Filter in High Temperature Chemical
Improving Process Control for Copper Electroplating through Filter Membrane Optimization
Particle – Wafer Interactions in Semiaqueous Silicon Cleaning Systems
III. Drying
Drying of High Aspect Ratio Structures: A Comparison of Drying Techniques via Electrical Stiction Analysis
Relationship between Atmospheric Humidity and Watermark Formation in IPA Dry of Si Wafer after HF Clean
IV. Metrology
Complementary Metrology within a European Joint Laboratory
Highly Sensitive Detection of Inorganic Contamination
Trace Metallic Contamination Analysis on Wafer Edge and Bevel by TXRF and VPD-TXRF
Surface Potential Difference Imaging Applied to Wet Clean Monitoring
V. Contamination Control
Metallic Contamination Control in Leading-Edge ULSI Manufacturing
Molybdenum Contamination in Silicon: Detection and Impact on Device Performances
Developing a High Volume Manufacturing Wet Clean Process to Remove BF2 Implant Induced Molybdenum Contamination
Impact of Metal-Ion Contaminated Silica Particles on Gate Oxide Integrity
Monitoring System for Airborne Molecular Contamination (AMC) in Semiconductor Manufacturing Areas and Micro-Environments
Reduction of Airborne Molecular Contamination on 300 mm Front Opening Unified POD (FOUP) and Wafers Surface by Vacuum Technology
Study of the Volatile Organic Contaminants Absorption and their Reversible Outgassing by FOUPs
Prevention of Condensation Defects on Contact Patterns by Improving Rinse Process
Single Wafer Ozone-Based Processing for Effective Edge Fluoropolymer Cleaning
Cleanliness Management in Advanced Microelectronic
VI. Front End of Line: Surface Preparation and Etching
Surface Preparation and Passivation of III-V Substrates for Future Ultra-High Speed, Low Power Logic Applications
Preparation and Characterization of Self-Assembled Monolayers on Germanium Surfaces
Application of Single-Wafer Wet Cleaning Prior to Epitaxial SiGe Process
Low Temperature Pre-Epi Treatment: Critical Parameters to Control Interface Contamination
Silicon Surface Preparation and Passivation by Vapor Phase of Heavy Water
Defects of Silicon Substrates Caused by Electro-Static Discharge in Single Wafer Cleaning Process
Three-Step Room Temperature Wet Cleaning Process for Silicon Substrate
Effect of Wet Treatment on Stability of Spin-On Dielectrics for STI Gap-Filling in Nanoscale Memory
Influence of Wet Cleaning on Tungsten Deposited with Different Techniques
VII. Front End of Line: Etching
Etch Rate Study of Germanium, GaAs and InGaAs: A Challenge in Semiconductor Processing
Poly-Silicon Etch with Diluted Ammonia: Application to Replacement Gate Integration Scheme
Advances on 45nm SiGe-Compatible NiPt Salicide Process
Impact of Galvanic Corrosion on Metal Gate Stacks
Photoresist Adhesion during Wet Etch on Single Wafer Tool
Surface Texturization and Interface Passivation of Mono-Crystalline Silicon Substrates by Wet Chemical Treatments
Mechanism of Plasma-Less Gaseous Etching Process for Damaged Oxides from the Ion Implantation Process
Current Advances in Anhydrous HF/Organic Solvent Processing of Semiconductor Surfaces
Co-Solvent Effect on the HF/CO2 Dry Etching of Sacrificial Oxides
A Novel Vapor Phase Etching Process for Si
VIII. Front End of Line: Post Ion Implantation Photo Resist Strip
Material Loss Impact on Device Performance for 32nm CMOS and Beyond
Evaluation of Plasma Strip Induced Substrate Damage
Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond
Influence of Dry Ashing and Wet Treatments on NVM Metal Gate Structures
Chemical and Mechanical Analysis of HDIS Residues Using Auger Electron Spectroscopy and Nanoindentation
Shortening of Plasma Strip Process Resulting in Better Removal of Photo Resist after High Dose Implantation
Stripping and Cleaning of High-Dose Ion-Implanted Photoresists Using a Single-Wafer, Single-Chamber Dry/Wet Hybrid System
Post Ion-Implant Photoresist Stripping Using Steam and Water: Pre-Treatment in a Steam Atmosphere and Steam-Water Mixed Spray
Steam-Injected SPM Process for All-Wet Stripping of Implanted Photoresist
Novel Methods for Wet Stripping High Dose Implanted Photoresist Using Sulfur Trioxide
All Wet Photoresist Strip by Solvent Aerosol Spray
Stripping of Ion Implanted Photoresist by CO2 Cryogenic Pre-Treatment Followed by Wet Cleaning
IX. Back End of Line: Post Dielectric Etch Photo Resist Strip
Porous Low-k Wet Etch in HF-Based Solutions: Focus on Cleaning Process Window, "Pore-Sealing" and "k Recovery"
Photoresist Removal Using Alternative Chemistries and Pressures
Ozone Chemistry for BEOL Resist Stripping – A Systematic Analytical Attempt to Understand the Interaction of O3 with Modern DUV-Resists
Design and Development of Novel Remover for Cu/Porous Low-k Interconnects
Surface Energy and Wetting Behaviour of Plasma Etched Porous SiCOH Surfaces and Plasma Etch Residue Cleaning Solutions
Modification of Photoresist by UV for Post-Etch Wet Strip Applications
Recyclable Fluorine-Based Cleaning Solvents for Resist Removal
Cu Dendrite Formation in Post Trench Etch Cleaning
The Interaction of Sublimed Iminodiacetic Acid with a Cu{110} Surface
Advances in Test Wafer Reclaim Technology – Wet Stripping Porous Low-k Films with No Substrate Damage
Electrochemical Behavior of Cobalt in Post-Via Etch Cleaning Solutions
X. Back End of Line: Post Metal Etch Photo Resist Strip
Characterization of Post Etch Residues Depending on Resist Removal Processes after Aluminum Etch
Impact of Dry Etch and Ash Conditions on Removability of Plasma Etch Residues in Al-Metallization. Approach to Improve PER Cleaning Efficiency by EHS-Friendly Aqueous Remover
Borderless via Clean Study for Minimizing Al-Cu Loss in 58nm Flash Devices
XI. Back End of Line: Post Cu CMP Cleaning
Effect of Various Cleaning Solutions and Brush Scrubber Kinematics on the Frictional Attributes of Post Copper CMP Cleaning Process
The Effect of PVA Brush Scrubbing on Post CMP Cleaning Process for Damascene Cu Interconnection
Cu Surface Characterization after Wet Cleaning Processes
Impact of CMP Polish and pCMP Cleaning on Adhesion of SiCN Capping Layer on PECVD-Derived Porous OSG and Copper
Damage-Free Post-CMP Cleaning Solution for Low-k Fluorocarbon on Advanced Interconnects
Process Dependence on Defectivity Count on Copper and Dielectric Surfaces in Post-Copper CMP Cleaning
A Novel Copper Interconnection Cleaning by Atomic Hydrogen Using Diluted Hydrogen Gas